1. Field of the Invention
The present invention relates to a clock supplying circuit, and in particular relates to an internal clock supplying circuit in an integrated circuit device such as a synchronous DRAM that operates synchronised with an external clock.
2. Description of the Related Art
Demands for increased speed of operation in recent years have led to the development of integrated circuit devices whose internal circuitry is operated in synchronism with a clock supplied from the system. Examples of such integrated circuit devices are synchronous DRAMs and RAM-bus DRAMs. In such integrated circuit devices, usually, an internal clock is generated on the basis of an external clock supplied from outside and synchronised internally with this external clock. High speed operation is feasible by controlling the internal circuits using this internal clock. In this case, since the propagation of the clock signal in the integrated circuit is subject to a certain delay, the internal circuit operation is aligned with the system timing by generating an internal clock that coincides with the phase of the external clock, taking into account this delay time.
FIG. 13 is a layout diagram of a synchronous DRAM. This memory 10 comprises: an address buffer 12 that latches address signals from outside, a decoder 14 that decodes the address signals, a driver 16 that drives a word line in accordance with the decoder output, a memory cell region 18, sense amplifier 20, bit selection circuit 22 and a plurality of output buffers 24-27.
In this example, output buffers 24-27 are supplied with internal clock I.sub.CLK and output data with the timing of this clock. A DLL (Delayed Lock Loop) circuit 30 is provided within the memory to align this output timing with the timing of the external clock E.sub.CLK supplied from the system. This DLL circuit 30 inputs the external clock E.sub.CLK and generates an internal clock I.sub.CLK taking into account the propagation delay time resulting from the resistance R1 and capacitance C of wiring 32 through which the internal clock signal is propagated. As a result, an internal clock I.sub.CLK whose phase coincides with that of external clock E.sub.CLK is supplied to output buffers 24-27.
However, as shown in FIG. 13, even if internal clock I.sub.CLK is supplied to the plurality of output buffers 24-27 so as to operate them with the same timing, due to the presence of resistances R2, R3, R4 of wiring 32 corresponding to the positions where these output buffers are disposed, the internal clocks I.sub.CLK1 -I.sub.CLK4 that are supplied to the respective output buffers 24-27 have different phases. In particular, if a large number of output buffers are arranged in a row, wiring 32 that supplies the internal clock becomes long, resulting in a considerable phase offset of the internal clock I.sub.CLK supplied at the output buffer that is nearest DLL circuit 30 and the output buffer that is furthest. Such "skewing" of the internal clock makes it impossible for all the output buffers to output data synchronously with external clock E.sub.CLK.
Likewise, there are provided for example a number of address buffer circuits 12 corresponding to the number of address signals. Thus, even if it is intended that the address signals are acquired and latched uniformly with the external clock timing, the internal clock phases supplied to the respective address buffer circuits are still offset. The same problem of skewing of the internal clock occurs likewise in effecting synchronisation at an arbitrary position in an integrated circuit such as for example a logic circuit or microprocessor in addition to memory.
Methods of eliminating this skewing of the internal clock include adopting a tree structure for the wiring from the clock driver and matching the timings at respective positions where the internal clock is supplied, or making the wirings whereby the clock is supplied all of the same length. However, all of these necessitate excess wiring and so constitute a factor lowering spatial efficiency.